Products -

Вернуться в раздел

IZ1308B

Pin to Pin Compatibility: LT1308B
Function: Microcircuit IZ1308В is a step up pulse voltage converter

IN18B20D*

Pin to Pin Compatibility: DS18B20
Function: Integrated circuit of digital sensor-measurer of temperature for industrial temperature range
Features: Measurement temperature range: from -55°C to +125°C Temperature value is converted to 12-bit digital code Accuracy of temperature indication can be programmed by customer form 9 to 12 bit Alarm signal for case of temperature excess of threshold values determined (programmed) by customer Unique 64-bit serial number for each IC, not available for changes by customer Data read/write operation from memory of IC,1-wire interface of data transfer
Pins (Pads): SO-8

Field P DMOS transistors

Application, features: MOSFET

Low-power

Vtn= 0,8-2,0V

Ubr=50-240V

Pmax=1,0 Watt

High-power

Vtn= 2,0-4,0V

Ubr=60-100V

Pmax=150 Watt
Process Description: Number of masks, pcs. 7-9 Min design rule,µm 3.0 Substrate: Si/B-doped/ p-type/Res 0,005 Epi layer: thickness (15-34) µm Resistivity (2÷21) Ohm/cm Gate oxide (42,5÷80) nm Interlayer dielectric medium temp. PSG Passivation: low temp. PSG

Field N DMOS transistors

Application, features: MOSFET

Low-power

Vtn= 0,6-3,0V

Ubr=50-200V

Pmax=1,0 Watt

High-power

Vtn= 2,0-4,0V

Ubr=50-600V

Pmax=200 Watt
Process Description: Number of masks, pcs. 7-9 Min design rule,µm 3.0 Substrate: Si/Sb-doped/ n-type/Res 0,01 Epi layer: Thickness (9÷42) µm Resistivity (0,7÷16) Ohm/cm Gate oxide (42,5÷80) nm Interlayer dielectric - medium temp. PSG Passivation: low temp. PSG

Power field MOS transistors, Umax= 60÷900 V, 150 mm wafers

Application, features: MOSFET NMOS: Vtn=2÷4 V Umax= 60÷900 V
Process Description: Number of masks, pcs. 8 Min design rule,µm 2.0 Substrate: Si/Sb-doped/ n-type/Res 0,015; Si/ As-doped/ n-type/ Res 0,003 Epi layer: thickness 8÷75) µm Resistivity (0,67÷31,5) Ohm/cm Gate oxide (60÷100) nm Interlayer dielectric medium temp. oxide + BPSG Passivation PEoxide + PE SI3N4

BiCDMOS, LOCOS isolation, 1 PolySi, 1 Me, NMOS/PMOS transistors

Application, features: Low-voltage transistors: NMOS: Vtn= 1.8 V, Usd >16 V PMOS: Vtp= 1.5 V, Usd >16 V NPN: h21e= 100-300 Resistors in layer: PolySi 1= 20-30 Ohm/sq High-voltage transistors : NDMOS: Vtn= 1.0÷1.8 V, Usd >=500 V PDMOS: Vtp= 0.7÷2.0 V, Usd >=700 V
Process Description: Number of masks, pcs. 15 Min design rule,µm 2.8 Substrate: Si/B-doped/ p-type/ Res 80 Isolation: LOCOS P-well depth, µm 6.5 N-well depth, µm 4.5 NDMOS base depth, µm 2.4 Gate SiO2, Å 600 Interlayer dielectric – Medium temp. PSG, µm 0,6 Channel length (gate): N/PMOS, µm 2.0 Contacts, µm 2.0x2.0 Space line Me 1, µm 8 Space line Me 2, µm 10

90 V, p-n junction isolation, 1 PolySi, 1 Me, NMOS/PMOS low-voltage transistors, NDMOS/PDMOS high-voltage lateral transistors, power vertical NDMOS transistor, bipolar vertical NPN & lateral PNP transistors

Application, features: Small and medium-scale integration analogue IC, VDD < 90 V NPN Vertical: bn =50 Uсе=20 V PNP Lateral: bр =25 Uсе=20 V LNDMOS: Vtn= 2.0 V, Usd >90 V LPDMOS: Vtp= -1.4 V, Usd >90 V NMOS: Vtn= 1.2 V, Usd >18 V PMOS: Vtp= 1.5 V, Usd >18 V VNDMOS: Vtn= 2.0 V, Usd >70 V Resistors in layer: NDMOS base, Р-drain, PolySi. Capacitors: PolySi-Si (SiO2 750Å) PolySi-Al (SiO2 8000 Å)
Process Description: Numberofmasks, pcs. 19 Min design rule,µm 4.0 Substrate: Si/B-doped/ p-type/ Thk 460/ Res 12/ (100) Buried layers: Si/Sb-doped/ n-type/Thk 20/Res 6; Si/B-doped/ p-type/Thk 250/Res2.0 ; Epi layer: Si/P-doped/ n-type/ Thk 10/ Res 1.5; Isolation: p-n junction P-well depth, µm 6.5 NDMOS base depth, µm 2.5 Gate SiO2, Å 750 NPN p-base depth, µm 2.5 N+emitter depth, µm 0.5 Interlayer dielectric - BPSG, µm 0,8 Channel length (gate): N/PMOS, µm Ø 4 Space line PolySi, µm 7 Contacts, µm 2 Space line Me, µm 8

BiCDMOS 600 V, p-n junction isolation, 1 PolySi, 1 Me

Application, features: SMPS-IC Low voltage NPN: h21E 50 min, Uсе 30V min PNP Lateral: h21E=2,2-30 Uсе=25-60 V NDMOS: Vtn=1.2-3.0 V, Usd >=30 V Low voltage PMOS: Vtp=0.8-2.0 V, Usd >=18 V High voltage PMOS: Vtp=0.8-2.0 V, Usd >=22 V Low voltage NMOS: Vtn=0.8-2.0 V, Usd >=18 V High voltage NMOS: Vtn=0.8-2.0 V, Usd >=600 V
Process Description: Number of masks, pcs. 15 Min design rule,µm 3.0 Substrate: Si/B-doped/ p-type/ Thk 460/ Res 60/ (100) Isolation: p-n junction NDMOS base depth, µm 2.5 Gate SiO2, Å 750 Interlayer dielectric – medium temp. PSG, µm 0,8

BiCDMOS 48 V, p-n junction isolation, 1 PolySi, 1 Me

Application, features: Power electronics actuator IC NPN Vertical: h21E=25-90 Uсе=20-70 V PNP Lateral: h21E=2,2-30 Uсе=25-60 V NDMOS: Vtn=1.8-2.6В, Usd=60-100 V Low voltage PMOS: Vtp=0.8-1.4 V, Usd =20-35 V High voltage PMOS: Vtp=1.2-2.2 V, Usd =30-80 V NMOS transistor: Vtn=1.1-1.7 V, Usd =15-25 V
Process Description: Number of masks, pcs. 16 Min design rule,µm 3.0 Substrate: Si/B-doped/ p-type/ Thk 460/ Res 12/ (100) Buried layers: Si/Sb-doped/ n-type/Thk 20/Res 6; Si/B-doped/ p-type/Thk 250/Res2.0 Epi layer: Si/P-doped/ n-type/ Thk 12/ Res 1.5; Isolation: p-n junction P-well depth, µm 5.0 Gate SiO2, Å 750 Interlayer dielectric – Medium temp. PSG, µm 0,8

200 V, p-n junction isolation, 1 PolySi, 1 Me, NDMOS/PDMOS, high-voltage transistors

Application, features: Small -scale integration analogue IC, VDD < 210 V NPN Vertical: bn =70 Uсе=50 V NDMOS: Vtn= 2.0 V, Usd >200 V PDMOS: Vtp= -1.0 V, Usd >200 V NMOS: Vtn= 1.5V, Usd >20V Resistors in layer: NPN base, Р-drain, PolySi. Capacitors: PolySi-Si (SiO2 900 Å) PolySi-Al (SiO2 1600 Å)
Process Description: Number of masks, pcs. 19 Min design rule,µm 4.0 Substrate: Si/B-doped/ p-type/ Thk 460/ Res 12/ (100) Buried layers: Si/Sb-doped/ n-type/Thk 30/Res 5.5; Si/B-doped/ p-type/Thk 300/Res2.0 ; Epi layer: Si/ P-doped/ n-type/ Thk 27/ Res 8.0; Isolation: p-n junction P-well depth, µm 6.5 NDMOS base depth, µm 3.0 Gate SiO2, Å 900 NPN p-base depth, µm 2.5 N+emitter depth, µm 0.8 Interlayer dielectric – medium temp. PSG 0,55mm +SIPOS 0.1µm + medium temp. PSG 1,1µm Channel length (gate): N/PDMOS, µm 6 Space line PolySi, µm 8 Contacts, µm Ø4 Space line Me, µm 12

8 V, 0.8 µm, BiCMOS, 3 Poly Si,2 Me, PolySi-emitters, 150mm wafers

Application, features: Analogue-digital IC for TV-receivers, Ucc=8V NMOS: Vtn=0.6 V, Usd >12 V PMOS: Vtр=-0.9 V, Usd >12 V NPN vertical: bn =120 Uce=10 V PNP lateral: bp =45 Uce=13 V
Process Description: Number of masks, pcs. 26 Design rule,µm 0.8 Substrate: Si/B-doped/ p-type/Res 3 Epitaxy: Si/P-doped/ n-type/ Thk 2.4/ Res 4.5 p-well depth with p+cc, µm 4.3 n-well depth with n+cc, µm 4.3 Gate SiO2, Å 130 Interlayer dielectric: BPSG Interlevel dielectric: PEoxide+ SOG NMOS/PMOS channel length, µm 0.9/1.0 N&P LDD- drains Me I Ti-TiN/Al-Si/TiN Me II Ti/Al-Si/TiN NPN emitter size, µm 1.2*3.2 Space line PolySi 2,µm 1.8 Contacts 1, µm Ø 0.9 Space line Me 1, µm 2.2 Contacts 2,µm Ø 0.9 Space line Me 2, µm 2.4

1.2 µm CMOS PROM, 2 PolySi, 2 Me, zappable link

Application, features: CMOS master-slice chip NMOS: Vtn=1.0 V, Ic >10 mA. Ubr>12V PMOS: Vtр=1.0 V, Ic >4.0 mA, Ubr>12V
Process Description: Number of masks, pcs. 11 Design rule,µm 1.2 Substrate: Si/B-doped / p-type/Res 12 N/P-well depth, µm 5/6 Gate SiO2, Å 250-300 Interlayer dielectric: BPSG Channel length: NMOS/PMOS, µm 2.0 Contacts, µm 2.0x2.0 Space line Me1, µm 8 Space line Me 2, µm 10

1.2 µm CMOS, 1 PolySi, 2 Me

Application, features: CMOS master-slice chip NMOS: Vtn=0.7 V, Ic >11.5 mA. Ubr>12V PMOS: Vtр=0.8 V, Ic >4.5 mA, Ubr>12V
Process Description: Number of masks, pcs. 11 Design rules,µm 1.2 Substrate: Si/B-doped/ p-type/Res 12 N/P-wells depth, µm 5/6 Gate SiO2, Å 250-300 Interlayer dielectric: BPSG Channel length: NMOS/PMOS, µm 1.4/1.6 Space line PolySi, µm 2.8 Contacts, µm 1.6x1.6 Space line Me1, µm 3.4 Space line Me2, µm 3

5 V, 3 µm CMOS, 1 PolySi, 1 Me

Application, features: Small and medium-scale integration logic IC, VDD < 5 V NMOS: Vtn=0.8-1.2 V, Ic >4 mA. Ubr>8V PMOS: Vtр=0.8-1.2 V, Ic >2 mA, Ubr>8V
Process Description: Number of masks, pcs. 11 Design rule,µm 2.0 Substrate: Si/P-doped/ n-type/Res 4.5 N/P-wells depth, µm 6-8 Gate SiO2, Å 425 / 300 Interlayer dielectric: BPSG Channel length: NMOS/PMOS, µm 3-4 Space line PolySi, µm 10 Contacts, µm 4*4 Space line Me, µm 10

1.5 V, 3.0 µm CMOS, 1 PolySi 1 Me, not self-aligned gate

Application, features: Clock/ watch IC of small and medium-scale integration, VDD < 1.5 V NMOS: Vtn=0.7/0.5 V, Usd >8 V, Ic>4mA PMOS: Vtр=-0.7 V/-0.5, Usd >8 V, Ic>2mA
Process Description: Number of masks, pcs. 9 Design rules,µm 3,0-5,0 Substrate: Si/P-doped/ n-type/Res 4.5 P-well depth, µm 6-8 Gate SiO2, Å 800 Interlayer dielectric: medium temp. PSG Channel length: NMOS/PMOS, µm 3 Space line PolySi, µm 10 Contacts , µm 5 Space line Me, µm 12

3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 200mm wafers

Application, features: IC for telephony, customized IC, VDD 3 V… 5 V NMOS: Vtn=0.6 V, Usd >10 V PMOS: Vtр=-0.7 V, Usd >10 V
Process Description: Number of masks, pcs. 14 (16) Design rule,µm 0.8 Substrate: Si/ P-doped/n-type/Res 4.5 or Si/B-doped/ p-type/Res 12; 2 wells N/P-wells depth, µm 4/4 Interlayer dielectric: SACVD SiO2 + PE (TEOS) 1,05 µm Gate SiO2, Å 130/160 NMOS/PMOS channel length, µm 0.9/1.0 N&P LDD- drains Me I Ti/AlCu/Ti/TiN Space line PolySi,µm 1.9 Contacts 1 (filled in by W), µm Ø 0.7 Space line Me 1, µm 2.2 Me2 Ti/AlCu Contacts 2 (filled in by W),µm Ø 0.7 Space line Me 2, µm 2.4

3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 150mm wafers

Application, features: IC for telephony, customized IC, VDD 3 V… 5 V NMOS: Vtn=0.6 V, Usd >10 V PMOS: Vtр=-0.7V, Usd >10 V
Process Description: Number of masks, pcs. 14 (16) Design rule,µm 0.8 Substrate: Si/P-doped/ n-type/Res 4.5 or Si/B-doped/ p-type/Res 12; 2 wells N/P-wells depth, µm 4/4 Interlayer dielectric: BPSG Gate SiO2, Å 130 /160 Channel length NMOS/PMOS, µm 0.9/1.0 N&P LDD- drains Me I Ti-TiN/Al-Si/TiN Space line PolySi, µm 1.9 Contacts 1, µm Ø 0.9 Space line Me 1 2.2Me 2 Al-Si/TiN Contacts 2,µm Ø 0.9 Space line Me 2, µm 2.4

5 V, 1.5 µm CMOS, 1 PolySi, 1 Ме, PolySi- resistors, 150mm wafers

Application, features: Supply voltage controllers NMOS: Vtn= 0.5 V, Usd >10 V PMOS: Vtp= 0.5V, Usd >10 V
Process Description: Number of masks, pcs. 17 Design rule,µm 1.5 Substrate: Si/B-doped/p-type/Res 12; 2 wells N/P-well depth, µm 5/6 P-type PolySi resistors Bipolar vertical NPN transistor Gate SiO2, Å 250 Interlayer dielectric: BPSG Channel length: NMOS/PMOS, µm 1.7 N&P LDD- drains Space line PolySi, µm 2.5 Contacts, µm Ø 1.3 Space line Me, µm 3.5

5 V, 1.5 µm CMOS, 1 PolySi, 1 Me, 150mm wafers

Application, features: Digital IMC, microcontrollers with VDD= 5V NMOS: Vtn= 0.6V, Usd >10 V PMOS: Vtp= 1.0V, Usd >13 V
Process Description: Number of masks, pcs. 16 Design rule,µm 1.5 Substrate: Si/B-doped/ p-type/Res 12 2 wells N/P-well depth, µm 5/6 Interlayer dielectric: BPSG Gate SiO2, Å 250 Interlayer dielectric: BPSG Transistor built in ROM Buried contacts Channel length: NMOS/PMOS, µm 1.5 N & P LDD- drains space line PolySi,µm 2.5 contacts, µm Ø 1.5 space line Me,µm 3.5

1.5 V, 1.6 µm CMOS, 1 PolySi, 1 Me, low threshold, 150mm wafers

Application, features: Medium-scale integration digital IC for electronic timepieces and micro calculators, VDD 1.5 V¸3 V. NMOS: Vtn= 0.5 V, Usd >10 V PMOS: Vtp= -0.5 V, Usd >10 V
Process Description: Number of masks, pcs. 11 Design rule,µm 1.6 Substrate: Si/ B-doped/ p-type/Res 12 2 wells N/P-well depth, µm 5/6 Gate SiO2, Å 300 Interlayer dielectric – BPSG Channel length: NMOS/PMOS, µm 2.0 space line PolySi , µm 3.2 contacts, µm Ø 1.5 space line Me, µm 3.6

5 V, 1.2 µm CMOS, 2 PolySi, 2 Me, low voltage EEPROM, 150 mm wafers

Application, features: LSI EEPROM, VDD:2,4 V… 6 V LV NMOS: Vtn=(0.4-0,8)V, Usd>=12 V LV PMOS: Vtр=-(0.5-0,9)V, Usd ≤-12 V HV- NMOS: Vtn=(0,3-0,6)V, Usd>=17 V HV- РMOS: Vtр=-(0,6-1,0)V, Usd ≤-15 V
Process Description: Number of masks, pcs. 3 (marked) Design rule, µm 1.2 Substrate: Si/B-doped/ p-type/Res 12, 2 wells N/P-well depth, µm 5/6 Gate SiO2: Low voltage transistors, Å 250 High voltage transistors, Å 350 Tunnel SiO2, Å 77 Interlayer dielectric-1: Si3N4, Å 350 Interlayer dielectric -2: BPSG, Å 7000 Interlevel dielectric: PEoxide+SOG+ PEoxide Channel length: Low voltage NMOS/PMOS, µm 1.4/1.6 High voltage NMOS/PMOS, µm 2.6/2.6 N & P LDD- drains Built-in transistors Space line PolySi 1, µm 3.2 Space line PolySi 2, contact free, µm 2.4 Space line PolySi 2, with contact, µm 4,6 Contacts-1, µm Ø 1.2 Space line Me 1, contact free, µm 3.2 Space line Me 2, with contact, µm 4,4 Contacts 2, µm Ø 1.4 Space line Me 2, contact free, µm 4.4 Space line Me 2, with contact, µm 4,8

5 V, 1.6 µm CMOS, 2 PolySi,1 Me, EEPROM, 150 mm wafers

Application, features: Medium-scale integration EEPROM, VDD:2,4 V… 6 V NMOS: Vtn=(0,65+-0,25)V, Usd >=12 V PMOS: Vtр=-(0,8+-0,2)V, Usd ≤-12 V HV- NMOS: Vtn=(0,45+0,15)V Usd³17 V HV- РMOS: Vtр=-(0,8+0,2)V Usd ≤-16 V
Process Description: Number of masks, pcs. 17 Design rule, µm 1.6 Substrate: Si/B-doped/p-type/Res 12 2 wells N/P-well depth, µm 5/6 Gate SiO2, Å 425 Tunnel SiO2, Å 77 Interlayer dielectric-1: Si3N4, Å 350 Interlayer dielectric -2: BPSG, Å 7000 Built-in transistors Channel length: NMOS/PMOS Low-voltage transistors, µm 2.4 High- voltage transistors, µm 3.6 Space line PolySi 1, µm 3.2 Space line PolySi 2, µm 4.2 Contacts, mm Ø 1.2 Space line Me, µm 4.4

5 V, 2 µm CMOS, 1 PolySi, 1 Me

Application, features: Small and medium-scale integration logic IC, VDD < 5 V NMOS: Vtn=0.6/ 0.5 V, Usd >12 V PMOS: Vtр=-0,7V/-0,5, Usd >14 V
Process Description: Number of masks, pcs. 11 Design rule, µm 2.0 Substrate: Si/ /n -type/ Phosphorus/Res 4.5, 2 wells N/P-well depth, µm 6/7 Gate SiO2, Å 425/300 Interlayer dielectric: BPSG Channel length: NMOS/PMOS, µm 2.5 Space line PolySi, µm 4.5 Contacts, µm 2.4*2.4 Space line Me, µm 8.5

5 V, 1.5 µm CMOS, 1 PolySi, 2 Me

Application, features: Small and medium-scale integration logic IC, VDD < 5 V NMOS: Vtn= 0.8 V, Usd >12 V PMOS: Vtp= -0.8 V, Usd >12 V
Process Description: Number of masks, pcs. 14 Design rule,µm 1.5 Substrate: Si/ P-doped/n-type/Res 4.5 N/P-well depth, µm 5/5 Interlayer dielectric: BPSG Interlevel dielectric: PE oxide Gate SiO2, Å 245 Channel length: NMOS/PMOS,µm 1.4/2.0 N LDD-drains space line PolySi , µm 3.4 contacts 1, µm 1.5*4.5 space line Me 1, µm 6.0 contacts 2, µm 3.0*4.5 space line Me 2, µm 9.5

15 V, 5.0 µm CMOS, 1 PolySi, 1 Me, not self-aligned gate

Application, features: Small and medium-scale integration logic IC, VDD < 20 V NMOS: Vtn= 1.1 V, Usd >27 V PMOS: Vtp= -1.0 V, Usd >29 V
Process Description: Number of masks, pcs. 9 Design rule,µm 5.0 Substrate: Si/P-doped/ n-type/Thk 460/Res 4.5 (100) P-well depth, µm 10 Gate SiO2, Å 950 Interlayer dielectric: medium temp. PSG Channel length: NMOS/PMOS, µm 5/6 space line PolySi,µm 5.5 contacts, µm Ø2 space line Me, µm 8

CMOS, 0.35 μm, 2 polySi, 3 metals, E2PROM option, 200 mm wafer

Application, features: Digital IC with EEPROM, Epitaxy =2.4¸6.0 V For low-voltage transistors NMOS: Vtn=0.5 V, Usd >7 V PMOS: Vtр=-0.6 V, Usd >7 V For high-voltage transistors Vtn=0.6 V, Usd >16 V PMOS: Vtр=-0.6 V, Usd >9 V
Process Description: Number of photolithographies, pcs. 27 Design rule, μm 0.35 Substrate: 725KDB0,015(100) Epitaxial layer: 15KDB12 2 wells Interlayer dielectric: SACVD SiO2 + PC TEOS, μm 1.05 μm Gate SiO2, Å 250 Tunnel oxide, Å 75 Capacitor dielectric Si3N4, Å 250 Channel length NMOS/PMOS, μm 0.35 for low-voltage transistors NMOS/PMOS, μm 2.5/1.0 for high-voltage transistors N&P LDD- drains Titanium silicide Metal I,2 Ti/AlCu / Ti /TiN Contacts 1 (W-filled) ø 0.5 Metal 1 pitch, μm 0.95 Metal 3 Ti/AlCu Contacts 2,3 (W-filled), μm ø 0.5 Metal 2 pitch, μm 1.1

CMOS, 0.35 μm, 2 polySi, 3 metals, 200 mm wafer

Application, features: Digital IC, Epitaxy =2.4¸6.0 V For 3.0 V NMOS: Vtn=0.6 V, Usd >5 V PMOS: Vtр=-0.6 V, Usd >5 V For 5.0 V NMOS: Vtn=1.0 V, Usd >8 V PMOS: Vtр=-0.9 V, Usd >8 V
Process Description: Number of photolithographies, pcs. 22 Design rule, μm 0.35 Substrate: 725KDB0,015(100) Epitaxial layer: 15KDB12 2 retrograde wells for high-voltage transistors 2 retrograde wells for low-voltage transistors Interlayer dielectric: SACVD SiO2 + PC TEOS, μm 1.05 μm Gate SiO2, Å 70 for low-voltage transistors 350 for high-voltage transistors Channel length NMOS/PMOS, μm 0.35 for low-voltage transistors NMOS/PMOS, μm 1.0 for high-voltage transistors N&P LDD- drains Titanium silicide Metal I,2 Ti/AlCu / Ti /TiN Contacts 1 (W-filled), μm ø 0.4 Metal 1 pitch, μm 0.95 Metal Ti/AlCu Contacts 2,3 (W-filled), μm ø 0.5 Metal 2 pitch, μm 1.1

CMOS, 0.35 μm, 1 polySi, 2 metals, 200 mm wafer

Application, features: Digital IC, highly-resistant, Epitaxy = 3 V NMOS: Vtn=0.6 V, Usd >5 V PMOS: Vtр=-0.6 V, Usd >5 V
Process Description: Number of photolithographies, pcs. 15 Design rule, μm 0.35 Substrate: 725KDB0,015(100) Epitaxial layer: 15KDB12 2 retrograde wells Interlayer dielectric: SACVD SiO2 + PC TEOS, μm 1.05 μm Gate SiO2, Å 70 Channel length NMOS/PMOS, μm 0.35 N&P LDD- drains Titanium silicide Metal I Ti/AlCu / Ti /TiN PolySi pitch, μm 0.8 Contacts 1 (W-filled), μm ø 0.5 Metal 1 pitch, μm 0.95 Metal 2 Ti/AlCu Contacts 2 (W-filled), μm ø 0.5 Metal 2 pitch, μm 1.1

CMOS, 0.35 μm, 1 polySi, 2 metals, 200 mm wafer

Application, features: Digital IC, highly-resistant, Epitaxy =5 V NMOS: Vtn=0.6 V, Usd >7 V PMOS: Vtр=-0.6 V, Usd >7 V
Process Description: Number of photolithographies, pcs.              14

Design rule, μm                                          0.35

Substrate:                             725KDB0,015(100)

Epitaxial layer:                                   15KDB12

2 retrograde wells

Interlayer dielectric:

SACVD SiO2 + PC TEOS, μm              1.05 μm

Gate SiO2, Å                                             120

Channel length

NMOS/PMOS, μm                                    0.6

N&P LDD- drains

Titanium silicide

Metal I                                     Ti/AlCu / Ti /TiN

PolySi pitch, μm                                        1.0

Contacts 1 (W-filled), μm                         ø 0.5

Metal 1 pitch, μm                                    0.95

Metal 2                                              Ti/AlCu

Contacts 2 (W-filled), μm                       ø 0.5

Metal 2 pitch, μm                                      1.2

КУ613Б

Pin to Pin Compatibility: ВТА208-800В
Gate Trigger Current, Igt, mA: ≤50
I2t, for Fusing, I2t, A2c: 21
Latching Current, IL, mA: ≤60
Off-State Leakage Current, Id,Ir,mA: ≤0.5
Package: TO-220
Peak Gate Current, Igm, A: 2
Repetitive Peak Off-State Voltages, V drm, Vrrm, V: 800
RMS On-State Current, It (RMS): 8

Products

Integrated circuits

Discrete Semiconductors

Base Technology Process

IZ1308B

IN18B20D*

Field P DMOS transistors

Field N DMOS transistors

Power field MOS transistors, Umax= 60÷900 V, 150 mm wafers

BiCDMOS, LOCOS isolation, 1 PolySi, 1 Me, NMOS/PMOS transistors

90 V, p-n junction isolation, 1 PolySi, 1 Me, NMOS/PMOS low-voltage transistors, NDMOS/PDMOS high-voltage lateral transistors, power vertical NDMOS transistor, bipolar vertical NPN & lateral PNP transistors

BiCDMOS 600 V, p-n junction isolation, 1 PolySi, 1 Me

BiCDMOS 48 V, p-n junction isolation, 1 PolySi, 1 Me

200 V, p-n junction isolation, 1 PolySi, 1 Me, NDMOS/PDMOS, high-voltage transistors

8 V, 0.8 µm, BiCMOS, 3 Poly Si,2 Me, PolySi-emitters, 150mm wafers

1.2 µm CMOS PROM, 2 PolySi, 2 Me, zappable link

1.2 µm CMOS, 1 PolySi, 2 Me

5 V, 3 µm CMOS, 1 PolySi, 1 Me

1.5 V, 3.0 µm CMOS, 1 PolySi 1 Me, not self-aligned gate

3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 200mm wafers

3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 150mm wafers

5 V, 1.5 µm CMOS, 1 PolySi, 1 Ме, PolySi- resistors, 150mm wafers

5 V, 1.5 µm CMOS, 1 PolySi, 1 Me, 150mm wafers

1.5 V, 1.6 µm CMOS, 1 PolySi, 1 Me, low threshold, 150mm wafers

5 V, 1.2 µm CMOS, 2 PolySi, 2 Me, low voltage EEPROM, 150 mm wafers

5 V, 1.6 µm CMOS, 2 PolySi,1 Me, EEPROM, 150 mm wafers

5 V, 2 µm CMOS, 1 PolySi, 1 Me

5 V, 1.5 µm CMOS, 1 PolySi, 2 Me

15 V, 5.0 µm CMOS, 1 PolySi, 1 Me, not self-aligned gate

CMOS, 0.35 μm, 2 polySi, 3 metals, E2PROM option, 200 mm wafer

CMOS, 0.35 μm, 2 polySi, 3 metals, 200 mm wafer

CMOS, 0.35 μm, 1 polySi, 2 metals, 200 mm wafer

CMOS, 0.35 μm, 1 polySi, 2 metals, 200 mm wafer

КУ613Б