15 V, 5.0 µm CMOS, 1 PolySi, 1 Me, not self-aligned gate

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15 V, 5.0 µm CMOS, 1 PolySi, 1 Me, not self-aligned gate

Specifications
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Parameter	Meaning
Application, features	Small and medium-scale integration logic IC, VDD < 20 V NMOS: Vtn= 1.1 V, Usd >27 V PMOS: Vtp= -1.0 V, Usd >29 V
Process Description	Number of masks, pcs. 9 Design rule,µm 5.0 Substrate: Si/P-doped/ n-type/Thk 460/Res 4.5 (100) P-well depth, µm 10 Gate SiO2, Å 950 Interlayer dielectric: medium temp. PSG Channel length: NMOS/PMOS, µm 5/6 space line PolySi,µm 5.5 contacts, µm Ø2 space line Me, µm 8

Parameter

Meaning

Application, features

Small and medium-scale integration logic IC, VDD < 20 V

NMOS: Vtn= 1.1 V, Usd >27 V

PMOS: Vtp= -1.0 V, Usd >29 V

Process Description

Number of masks, pcs.                                           9

Design rule,µm                                                    5.0

Substrate: Si/P-doped/ n-type/Thk 460/Res 4.5 (100)

P-well depth, µm                                                   10

Gate SiO2, Å                                                        950

Interlayer dielectric:                    medium temp. PSG

Channel length: NMOS/PMOS, µm                      5/6

space line PolySi,µm                                            5.5

contacts, µm                                                           Ø2

space line Me, µm                                                   8

To order

The order, cost and terms of fulfillment of orders for the supply of small-scale batches of products are additionally agreed by the Consumer with the marketing and sales services of OJSC "INTEGRAL" - the management company of the holding "INTEGRAL"

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Tel.: .....(+375 17) 272 3729
......(+375 17) 353 2257
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E-mail: export@integral.by