15 V, 5.0 µm CMOS, 1 PolySi, 1 Me, not self-aligned gate

15 V, 5.0 µm CMOS, 1 PolySi, 1 Me, not self-aligned gate

15 V, 5.0 µm CMOS, 1 PolySi, 1 Me, not self-aligned gate
  • Application, features: Small and medium-scale integration logic IC, VDD < 20 V<br /><br /> <br /><br />NMOS: Vtn= 1.1 V, Usd >27 V<br /><br />PMOS: Vtp= -1.0 V, Usd >29 V
  • Process Description: Number of masks, pcs.                                           9<br /><br />Design rule,µm                                                    5.0<br /><br />Substrate: Si/P-doped/ n-type/Thk 460/Res 4.5 (100)                                                <br /><br />P-well depth, µm                                                   10<br /><br />Gate SiO2, Å                                                        950<br /><br />Interlayer dielectric:                    medium temp. PSG<br /><br />Channel length: NMOS/PMOS, µm                      5/6<br /><br />space line PolySi,µm                                            5.5<br /><br />contacts, µm                                                           Ø2<br /><br />space line  Me, µm                                                   8