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3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 150mm wafers

3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 150mm wafers

Parameter Meaning
Application, features IC for telephony,

customized IC, VDD 3 V… 5  V

 

NMOS: 

Vtn=0.6 V, Usd >10 V

PMOS: 

Vtр=-0.7V, Usd >10 V
Process Description Number of masks, pcs.                                 14 (16)

Design rule,µm                                                 0.8

Substrate: Si/P-doped/ n-type/Res 4.5

or Si/B-doped/ p-type/Res 12;                      2 wells

N/P-wells depth, µm                                           4/4

Interlayer dielectric:                                       BPSG

Gate SiO2, Å                                             130 /160

Channel length NMOS/PMOS, µm               0.9/1.0

N&P LDD- drains

Me I                                               Ti-TiN/Al-Si/TiN

Space line PolySi, µm                                         1.9

Contacts 1, µm                                                Ø 0.9

Space line Me 1   2.2Me 2                       Al-Si/TiN

Contacts 2,µm                                                 Ø 0.9

Space line Me 2, µm                                           2.4
The order, cost and terms of fulfillment of orders for the supply of small-scale batches of products are additionally agreed by the Consumer with the marketing and sales services of OJSC "INTEGRAL" - the management company of the holding "INTEGRAL"

Marketing & Sales Department
Tel.: .....(+375 17) 272 3729
       ......(+375 17) 353 2257
Fax:......(+375 17) 353 2257
E-mail: export@integral.by

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