3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 150mm wafers
3-5 V, 0.8 µm CMOS, 1 PolySi (2 PolySi), 2 Me, 150mm wafers
- Application, features: IC for telephony,<br /><br />customized IC, VDD 3 V… 5 V<br /><br /> <br /><br />NMOS: <br /><br />Vtn=0.6 V, Usd >10 V<br /><br />PMOS: <br /><br />Vtр=-0.7V, Usd >10 V
- Process Description: Number of masks, pcs. 14 (16)<br /><br />Design rule,µm 0.8<br /><br />Substrate: Si/P-doped/ n-type/Res 4.5<br /><br />or Si/B-doped/ p-type/Res 12; 2 wells<br /><br />N/P-wells depth, µm 4/4<br /><br />Interlayer dielectric: BPSG<br /><br />Gate SiO2, Å 130 /160<br /><br />Channel length NMOS/PMOS, µm 0.9/1.0<br /><br />N&P LDD- drains<br /><br />Me I Ti-TiN/Al-Si/TiN<br /><br />Space line PolySi, µm 1.9<br /><br />Contacts 1, µm Ø 0.9<br /><br />Space line Me 1 2.2Me 2 Al-Si/TiN<br /><br />Contacts 2,µm Ø 0.9<br /><br />Space line Me 2, µm 2.4