1.2 µm CMOS PROM, 2 PolySi, 2 Me, zappable link

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CMOS processes

1.2 µm CMOS PROM, 2 PolySi, 2 Me, zappable link

Specifications
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Parameter	Meaning
Application, features	CMOS master-slice chip NMOS: Vtn=1.0 V, Ic >10 mA. Ubr>12V PMOS: Vtр=1.0 V, Ic >4.0 mA, Ubr>12V
Process Description	Number of masks, pcs. 11 Design rule,µm 1.2 Substrate: Si/B-doped / p-type/Res 12 N/P-well depth, µm 5/6 Gate SiO2, Å 250-300 Interlayer dielectric: BPSG Channel length: NMOS/PMOS, µm 2.0 Contacts, µm 2.0x2.0 Space line Me1, µm 8 Space line Me 2, µm 10

Parameter

Meaning

Application, features

CMOS master-slice chip

NMOS:

Vtn=1.0 V, Ic >10 mA. Ubr>12V

PMOS:

Vtр=1.0 V, Ic >4.0 mA, Ubr>12V

Process Description

Number of masks, pcs.                                              11

Design rule,µm                                                        1.2

Substrate:                            Si/B-doped / p-type/Res 12

N/P-well depth, µm                                                  5/6

Gate SiO2, Å                                                    250-300

Interlayer dielectric:                                            BPSG

Channel length: NMOS/PMOS, µm                         2.0

Contacts, µm                                                     2.0x2.0

Space line Me1, µm                                                    8

Space line Me 2, µm                                                  10

To order

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