5 V, 2 µm CMOS, 1 PolySi, 1 Me

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CMOS processes

5 V, 2 µm CMOS, 1 PolySi, 1 Me

Specifications
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Parameter	Meaning
Application, features	Small and medium-scale integration logic IC, VDD < 5 V NMOS: Vtn=0.6/ 0.5 V, Usd >12 V PMOS: Vtр=-0,7V/-0,5, Usd >14 V
Process Description	Number of masks, pcs. 11 Design rule, µm 2.0 Substrate: Si/ /n -type/ Phosphorus/Res 4.5, 2 wells N/P-well depth, µm 6/7 Gate SiO2, Å 425/300 Interlayer dielectric: BPSG Channel length: NMOS/PMOS, µm 2.5 Space line PolySi, µm 4.5 Contacts, µm 2.4*2.4 Space line Me, µm 8.5

Parameter

Meaning

Application, features

Small and medium-scale integration logic IC, VDD < 5 V

NMOS: Vtn=0.6/ 0.5 V, Usd >12 V

PMOS: Vtр=-0,7V/-0,5, Usd >14 V

Process Description

Number of masks, pcs.                                                     11

Design rule, µm                                                              2.0

Substrate: Si/ /n -type/ Phosphorus/Res 4.5,           2 wells

N/P-well depth, µm                                                        6/7

Gate SiO2, Å                                                           425/300

Interlayer dielectric:                                                   BPSG

Channel length: NMOS/PMOS, µm                               2.5

Space line PolySi, µm                                                    4.5

Contacts, µm                                                            2.4*2.4

Space line Me, µm                                                          8.5

To order

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Tel.: .....(+375 17) 272 3729
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E-mail: export@integral.by