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CMOS, 0.35 μm, 1 polySi, 2 metals, 200 mm wafer

CMOS, 0.35 μm, 1 polySi, 2 metals, 200 mm wafer

Parameter Meaning
Application, features Digital IC, highly-resistant,
Epitaxy = 3 V

 

NMOS: Vtn=0.6 V, Usd >5 V

PMOS: Vtр=-0.6 V, Usd >5 V
Process Description Number of photolithographies, pcs.               15

Design rule, μm                                        0.35

Substrate:                           725KDB0,015(100)

Epitaxial layer:                                  15KDB12

2 retrograde wells

Interlayer dielectric:

SACVD SiO2 + PC TEOS, μm             1.05 μm

Gate SiO2, Å                                              70

Channel length

NMOS/PMOS, μm                                   0.35

N&P LDD- drains

Titanium silicide

Metal I                                   Ti/AlCu / Ti /TiN

PolySi pitch, μm                                       0.8

Contacts 1 (W-filled), μm                        ø 0.5

Metal 1 pitch, μm                                    0.95

Metal 2                                              Ti/AlCu

Contacts 2 (W-filled), μm                        ø 0.5

Metal 2 pitch, μm                                      1.1
The order, cost and terms of fulfillment of orders for the supply of small-scale batches of products are additionally agreed by the Consumer with the marketing and sales services of OJSC "INTEGRAL" - the management company of the holding "INTEGRAL"

Marketing & Sales Department
Tel.: .....(+375 17) 272 3729
       ......(+375 17) 353 2257
Fax:......(+375 17) 353 2257
E-mail: export@integral.by

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