5 V, 1.5 µm CMOS, 1 PolySi, 1 Me, 150mm wafers
Parameter | Meaning |
---|---|
Application, features | Digital IMC, microcontrollers with VDD= 5V NMOS: Vtn= 0.6V, Usd >10 V PMOS: Vtp= 1.0V, Usd >13 V |
Process Description | Number of masks, pcs. 16 Design rule,µm 1.5 Substrate: Si/B-doped/ p-type/Res 12 2 wells N/P-well depth, µm 5/6 Interlayer dielectric: BPSG Gate SiO2, Å 250 Interlayer dielectric: BPSG Transistor built in ROM Buried contacts Channel length: NMOS/PMOS, µm 1.5 N & P LDD- drains space line PolySi,µm 2.5 contacts, µm Ø 1.5 space line Me,µm 3.5 |
The order, cost and terms of fulfillment of orders for the supply of small-scale batches of products are additionally agreed by the Consumer with the marketing and sales services of OJSC "INTEGRAL" - the management company of the holding "INTEGRAL"
Marketing & Sales Department
Tel.: .....(+375 17) 272 3729
......(+375 17) 353 2257
Fax:......(+375 17) 353 2257
E-mail: export@integral.by
Tel.: .....(+375 17) 272 3729
......(+375 17) 353 2257
Fax:......(+375 17) 353 2257
E-mail: export@integral.by