BiCDMOS, LOCOS isolation, 1 PolySi, 1 Me, NMOS/PMOS transistors

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Bipolar CDMOS processes

BiCDMOS, LOCOS isolation, 1 PolySi, 1 Me, NMOS/PMOS transistors

Specifications
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Parameter	Meaning
Application, features	Low-voltage transistors: NMOS: Vtn= 1.8 V, Usd >16 V PMOS: Vtp= 1.5 V, Usd >16 V NPN: h21e= 100-300 Resistors in layer: PolySi 1= 20-30 Ohm/sq High-voltage transistors : NDMOS: Vtn= 1.0÷1.8 V, Usd >=500 V PDMOS: Vtp= 0.7÷2.0 V, Usd >=700 V
Process Description	Number of masks, pcs. 15 Min design rule,µm 2.8 Substrate: Si/B-doped/ p-type/ Res 80 Isolation: LOCOS P-well depth, µm 6.5 N-well depth, µm 4.5 NDMOS base depth, µm 2.4 Gate SiO2, Å 600 Interlayer dielectric – Medium temp. PSG, µm 0,6 Channel length (gate): N/PMOS, µm 2.0 Contacts, µm 2.0x2.0 Space line Me 1, µm 8 Space line Me 2, µm 10

Parameter

Meaning

Application, features

Low-voltage transistors:

NMOS: Vtn= 1.8 V, Usd >16 V

PMOS: Vtp= 1.5 V, Usd >16 V

NPN: h21e= 100-300

Resistors in layer:

PolySi 1= 20-30 Ohm/sq

High-voltage transistors :

NDMOS: Vtn= 1.0÷1.8 V, Usd >=500 V

PDMOS: Vtp= 0.7÷2.0 V, Usd >=700 V

Process Description

Number of masks, pcs.                                             15

Min design rule,µm                                             2.8

Substrate:                                   Si/B-doped/ p-type/ Res 80

Isolation:                                                                   LOCOS

P-well depth, µm                                                     6.5

N-well depth, µm                                                     4.5

NDMOS base depth, µm                                         2.4

Gate SiO2, Å                                                           600

Interlayer dielectric – Medium temp. PSG, µm       0,6

Channel length (gate): N/PMOS, µm                     2.0

Contacts, µm                                                    2.0x2.0

Space line Me 1, µm                                                 8

Space line Me 2, µm                                                10

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