• Application, features: Low-voltage transistors:<br /><br />NMOS: Vtn= 1.8 V, Usd >16 V<br /><br />PMOS: Vtp= 1.5 V, Usd >16 V<br /><br />NPN: h21e= 100-300<br /><br />Resistors in layer:<br /><br />PolySi 1= 20-30 Ohm/sq<br /><br /> <br /><br />High-voltage transistors :<br /><br />NDMOS: Vtn= 1.0÷1.8 V, Usd >=500 V<br /><br />PDMOS: Vtp= 0.7÷2.0 V, Usd >=700 V
• Process Description: Number of masks, pcs.                                             15<br /><br />Min design rule,µm                                             2.8<br /><br />Substrate:                                   Si/B-doped/ p-type/ Res 80<br /><br />Isolation:                                                                   LOCOS<br /><br />P-well depth, µm                                                     6.5<br /><br />N-well depth, µm                                                     4.5<br /><br />NDMOS base depth, µm                                         2.4<br /><br />Gate SiO2, Å                                                           600<br /><br />Interlayer dielectric – Medium temp. PSG, µm       0,6                           <br /><br />Channel length (gate): N/PMOS, µm                     2.0<br /><br />Contacts, µm                                                    2.0x2.0<br /><br />Space line Me 1, µm                                                 8<br /><br />Space line Me 2, µm                                                10