BiCDMOS 48 V, p-n junction isolation, 1 PolySi, 1 Me

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BiCDMOS 48 V, p-n junction isolation, 1 PolySi, 1 Me

Specifications
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Parameter	Meaning
Application, features	Power electronics actuator IC NPN Vertical: h21E=25-90 Uсе=20-70 V PNP Lateral: h21E=2,2-30 Uсе=25-60 V NDMOS: Vtn=1.8-2.6В, Usd=60-100 V Low voltage PMOS: Vtp=0.8-1.4 V, Usd =20-35 V High voltage PMOS: Vtp=1.2-2.2 V, Usd =30-80 V NMOS transistor: Vtn=1.1-1.7 V, Usd =15-25 V
Process Description	Number of masks, pcs. 16 Min design rule,µm 3.0 Substrate: Si/B-doped/ p-type/ Thk 460/ Res 12/ (100) Buried layers: Si/Sb-doped/ n-type/Thk 20/Res 6; Si/B-doped/ p-type/Thk 250/Res2.0 Epi layer: Si/P-doped/ n-type/ Thk 12/ Res 1.5; Isolation: p-n junction P-well depth, µm 5.0 Gate SiO2, Å 750 Interlayer dielectric – Medium temp. PSG, µm 0,8

Parameter

Meaning

Application, features

Power electronics actuator IC

NPN Vertical:

h21E=25-90 Uсе=20-70 V

PNP Lateral:

h21E=2,2-30 Uсе=25-60 V

NDMOS: Vtn=1.8-2.6В, Usd=60-100 V

Low voltage PMOS:

Vtp=0.8-1.4 V, Usd =20-35 V

High voltage PMOS:

Vtp=1.2-2.2 V, Usd =30-80 V

NMOS transistor:

Vtn=1.1-1.7 V, Usd =15-25 V

Process Description

Number of masks, pcs.                                               16

Min design rule,µm                                                      3.0

Substrate:            Si/B-doped/ p-type/ Thk 460/ Res 12/ (100)

Buried layers:                  Si/Sb-doped/ n-type/Thk 20/Res 6;

                                       Si/B-doped/ p-type/Thk 250/Res2.0

Epi layer:                      Si/P-doped/ n-type/ Thk 12/ Res 1.5;

Isolation:                                                        p-n junction

P-well depth, µm                                                          5.0

Gate SiO2, Å                                                                750

Interlayer dielectric – Medium temp. PSG, µm       0,8

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