BiCDMOS 600 V, p-n junction isolation, 1 PolySi, 1 Me

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Bipolar CDMOS processes

BiCDMOS 600 V, p-n junction isolation, 1 PolySi, 1 Me

Specifications
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Parameter	Meaning
Application, features	SMPS-IC Low voltage NPN: h21E 50 min, Uсе 30V min PNP Lateral: h21E=2,2-30 Uсе=25-60 V NDMOS: Vtn=1.2-3.0 V, Usd >=30 V Low voltage PMOS: Vtp=0.8-2.0 V, Usd >=18 V High voltage PMOS: Vtp=0.8-2.0 V, Usd >=22 V Low voltage NMOS: Vtn=0.8-2.0 V, Usd >=18 V High voltage NMOS: Vtn=0.8-2.0 V, Usd >=600 V
Process Description	Number of masks, pcs. 15 Min design rule,µm 3.0 Substrate: Si/B-doped/ p-type/ Thk 460/ Res 60/ (100) Isolation: p-n junction NDMOS base depth, µm 2.5 Gate SiO2, Å 750 Interlayer dielectric – medium temp. PSG, µm 0,8

Parameter

Meaning

Application, features

SMPS-IC

Low voltage NPN:

h21E 50 min, Uсе 30V min

PNP Lateral:

h21E=2,2-30 Uсе=25-60 V

NDMOS: Vtn=1.2-3.0 V, Usd >=30 V

Low voltage PMOS:

Vtp=0.8-2.0 V, Usd >=18 V

High voltage PMOS:

Vtp=0.8-2.0 V, Usd >=22 V

Low voltage NMOS:

Vtn=0.8-2.0 V, Usd >=18 V

High voltage NMOS:

Vtn=0.8-2.0 V, Usd >=600 V

Process Description

Number of masks, pcs.                                              15

Min design rule,µm                                                     3.0

Substrate:           Si/B-doped/ p-type/ Thk 460/ Res 60/ (100)

Isolation:                                                        p-n junction

NDMOS base depth, µm                                             2.5

Gate SiO2, Å                                                                750

Interlayer dielectric – medium temp. PSG, µm       0,8

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