DMOS processes

	Part number	Function	Cд, пФ	Cв, пФ	fгр, МГц	Application, features	Process Description	Functions: 12H/24H	H1xV1xT1	h21е	H2xV2	H3xV3	h тока	Vb, b2 max, V	VCB max, V	Vcc	VCE max, V
	Field P DMOS transistors	уцауцацуацуа	3	3	33	MOSFET Low-power Vtn= 0,8-2,0V Ubr=50-240V Pmax=1,0 Watt High-power Vtn= 2,0-4,0V Ubr=60-100V Pmax=150 Watt	Number of masks, pcs. 7-9 Min design rule,µm 3.0 Substrate: Si/B-doped/ p-type/Res 0,005 Epi layer: thickness (15-34) µm Resistivity (2÷21) Ohm/cm Gate oxide (42,5÷80) nm Interlayer dielectric medium temp. PSG Passivation: low temp. PSG	4	3	3	33	3	3	4	4	4	4
Field P DMOS transistors Specifications Tech. support
	Field N DMOS transistors					MOSFET Low-power Vtn= 0,6-3,0V Ubr=50-200V Pmax=1,0 Watt High-power Vtn= 2,0-4,0V Ubr=50-600V Pmax=200 Watt	Number of masks, pcs. 7-9 Min design rule,µm 3.0 Substrate: Si/Sb-doped/ n-type/Res 0,01 Epi layer: Thickness (9÷42) µm Resistivity (0,7÷16) Ohm/cm Gate oxide (42,5÷80) nm Interlayer dielectric - medium temp. PSG Passivation: low temp. PSG
Field N DMOS transistors Specifications Tech. support
	Power field MOS transistors, Umax= 60÷900 V, 150 mm wafers					MOSFET NMOS: Vtn=2÷4 V Umax= 60÷900 V	Number of masks, pcs. 8 Min design rule,µm 2.0 Substrate: Si/Sb-doped/ n-type/Res 0,015; Si/ As-doped/ n-type/ Res 0,003 Epi layer: thickness 8÷75) µm Resistivity (0,67÷31,5) Ohm/cm Gate oxide (60÷100) nm Interlayer dielectric medium temp. oxide + BPSG Passivation PEoxide + PE SI3N4
Power field MOS transistors, Umax= 60÷900 V, 150 mm wafers Specifications Tech. support