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CMOS, 0.35 μm, 2 polySi, 3 metals, E2PROM option, 200 mm wafer

CMOS, 0.35 μm, 2 polySi, 3 metals, E2PROM option, 200 mm wafer

Parameter Meaning
Application, features Digital IC with EEPROM,

Epitaxy =2.4¸6.0 V

For low-voltage transistors

NMOS: 

Vtn=0.5 V, Usd >7 V

PMOS: 

Vtр=-0.6 V, Usd >7 V

For high-voltage transistors

Vtn=0.6 V, Usd >16 V

PMOS: 

Vtр=-0.6 V, Usd >9 V
Process Description Number of photolithographies, pcs.               27

Design rule, μm                                        0.35

Substrate:                           725KDB0,015(100)

Epitaxial layer:                                  15KDB12

2 wells

Interlayer dielectric:

SACVD SiO2 + PC TEOS, μm            1.05 μm

Gate SiO2, Å                                           250

Tunnel oxide, Å                                          75

Capacitor dielectric                   Si3N4, Å    250

Channel length

NMOS/PMOS, μm     0.35 for low-voltage

                                    transistors

NMOS/PMOS, μm     2.5/1.0 for high-voltage

                                    transistors                                              

N&P LDD- drains

Titanium silicide

Metal I,2                               Ti/AlCu / Ti /TiN

Contacts 1 (W-filled)                              ø 0.5

Metal 1 pitch, μm                                    0.95

Metal 3                                              Ti/AlCu

Contacts 2,3 (W-filled), μm                     ø 0.5

Metal 2 pitch, μm                                      1.1
The order, cost and terms of fulfillment of orders for the supply of small-scale batches of products are additionally agreed by the Consumer with the marketing and sales services of OJSC "INTEGRAL" - the management company of the holding "INTEGRAL"

Marketing & Sales Department
Tel.: .....(+375 17) 272 3729
       ......(+375 17) 353 2257
Fax:......(+375 17) 353 2257
E-mail: export@integral.by

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