• Application, features: CMOS master-slice chip<br /><br /> NMOS: <br /><br />Vtn=0.7 V, Ic >11.5 mA. Ubr>12V<br /><br />PMOS: <br /><br />Vtр=0.8 V, Ic >4.5 mA, Ubr>12V
• Process Description: Number of masks, pcs.                                          11<br /><br />Design rules,µm                                                   1.2<br /><br />Substrate:                        Si/B-doped/ p-type/Res 12<br /><br />N/P-wells depth, µm                                             5/6<br /><br />Gate SiO2, Å                                                     250-300<br /><br />Interlayer dielectric:                                              BPSG<br /><br />Channel length: NMOS/PMOS, µm                    1.4/1.6<br /><br />Space line PolySi, µm                                               2.8<br /><br />Contacts, µm                                                      1.6x1.6<br /><br />Space line Me1, µm                                                  3.4<br /><br />Space line Me2, µm                                                  3