1.2 µm CMOS, 1 PolySi, 2 Me

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CMOS processes

1.2 µm CMOS, 1 PolySi, 2 Me

Specifications
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Parameter	Meaning
Application, features	CMOS master-slice chip NMOS: Vtn=0.7 V, Ic >11.5 mA. Ubr>12V PMOS: Vtр=0.8 V, Ic >4.5 mA, Ubr>12V
Process Description	Number of masks, pcs. 11 Design rules,µm 1.2 Substrate: Si/B-doped/ p-type/Res 12 N/P-wells depth, µm 5/6 Gate SiO2, Å 250-300 Interlayer dielectric: BPSG Channel length: NMOS/PMOS, µm 1.4/1.6 Space line PolySi, µm 2.8 Contacts, µm 1.6x1.6 Space line Me1, µm 3.4 Space line Me2, µm 3

Parameter

Meaning

Application, features

CMOS master-slice chip

NMOS:

Vtn=0.7 V, Ic >11.5 mA. Ubr>12V

PMOS:

Vtр=0.8 V, Ic >4.5 mA, Ubr>12V

Process Description

Number of masks, pcs.                                          11

Design rules,µm                                                  1.2

Substrate:                        Si/B-doped/ p-type/Res 12

N/P-wells depth, µm                                            5/6

Gate SiO2, Å                                                     250-300

Interlayer dielectric:                                              BPSG

Channel length: NMOS/PMOS, µm                   1.4/1.6

Space line PolySi, µm                                               2.8

Contacts, µm                                                      1.6x1.6

Space line Me1, µm                                                  3.4

Space line Me2, µm                                                  3

To order

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