Field N DMOS transistors

Main

Products

Base Technology Process

DMOS processes

Field N DMOS transistors

Specifications
Purchase and tech. support

Parameter	Meaning
Application, features	MOSFET Low-power Vtn= 0,6-3,0V Ubr=50-200V Pmax=1,0 Watt High-power Vtn= 2,0-4,0V Ubr=50-600V Pmax=200 Watt
Process Description	Number of masks, pcs. 7-9 Min design rule,µm 3.0 Substrate: Si/Sb-doped/ n-type/Res 0,01 Epi layer: Thickness (9÷42) µm Resistivity (0,7÷16) Ohm/cm Gate oxide (42,5÷80) nm Interlayer dielectric - medium temp. PSG Passivation: low temp. PSG

Parameter

Meaning

Application, features

MOSFET

Low-power

Vtn= 0,6-3,0V

Ubr=50-200V

Pmax=1,0 Watt

High-power

Vtn= 2,0-4,0V

Ubr=50-600V

Pmax=200 Watt

Process Description

Number of masks, pcs.                                              7-9

Min design rule,µm                                                      3.0

Substrate:                        Si/Sb-doped/ n-type/Res 0,01

Epi layer:

Thickness                                                          (9÷42) µm

Resistivity                                              (0,7÷16) Ohm/cm

Gate oxide                                                    (42,5÷80) nm

Interlayer dielectric -                       medium temp. PSG

Passivation:                                               low temp. PSG

To order

The order, cost and terms of fulfillment of orders for the supply of small-scale batches of products are additionally agreed by the Consumer with the marketing and sales services of OJSC "INTEGRAL" - the management company of the holding "INTEGRAL"

Marketing & Sales Department
Tel.: .....(+375 17) 272 3729
......(+375 17) 353 2257
Fax:......(+375 17) 353 2257
E-mail: export@integral.by