• Application, features: Digital IC, highly-resistant,<br />Epitaxy =5 V<br /><br /> <br /><br />NMOS: Vtn=0.6 V, Usd >7 V<br /><br />PMOS: Vtр=-0.6 V, Usd >7 V
• Process Description: Number of photolithographies, pcs.              14
  
  Design rule, μm                                          0.35
  
  Substrate:                             725KDB0,015(100)
  
  Epitaxial layer:                                   15KDB12
  
  2 retrograde wells
  
  Interlayer dielectric:
  
  SACVD SiO2 + PC TEOS, μm              1.05 μm                                  
  
  Gate SiO2, Å                                             120
  
  Channel length
  
  NMOS/PMOS, μm                                     0.6
  
  N&P LDD- drains
  
  Titanium silicide
  
  Metal I                                     Ti/AlCu / Ti /TiN
  
  PolySi pitch, μm                                        1.0
  
  Contacts 1 (W-filled), μm                         ø 0.5
  
  Metal 1 pitch, μm                                    0.95
  
  Metal 2                                              Ti/AlCu
  
  Contacts 2 (W-filled), μm                       ø 0.5
  
  Metal 2 pitch, μm                                      1.2