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Application, features:
Small -scale integration analogue IC, <br /><br />VDD < 210 V<br /><br /> <br /><br />NPN Vertical:<br /><br />bn =70 Uсе=50 V<br /><br />NDMOS: Vtn= 2.0 V,<br /><br />Usd >200 V<br /><br />PDMOS: Vtp= -1.0 V,<br /><br />Usd >200 V<br /><br />NMOS: Vtn= 1.5V, Usd >20V<br /><br /> <br /><br />Resistors in layer:<br /><br />NPN base, Р-drain, PolySi.<br /><br /> <br /><br />Capacitors: PolySi-Si (SiO2 900 Å)<br /><br />PolySi-Al (SiO2 1600 Å)
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Process Description:
Number of masks, pcs. 19<br /><br />Min design rule,µm 4.0<br /><br />Substrate: Si/B-doped/ p-type/ Thk 460/ Res 12/ (100)<br /><br />Buried layers: Si/Sb-doped/ n-type/Thk 30/Res 5.5;<br /><br /> Si/B-doped/ p-type/Thk 300/Res2.0 ; <br /><br />Epi layer: Si/ P-doped/ n-type/ Thk 27/ Res 8.0;<br /><br />Isolation: p-n junction<br /><br />P-well depth, µm 6.5<br /><br />NDMOS base depth, µm 3.0<br /><br />Gate SiO2, Å 900<br /><br />NPN p-base depth, µm 2.5<br /><br />N+emitter depth, µm 0.8<br /><br />Interlayer dielectric – medium temp. PSG<br /><br />0,55mm +SIPOS 0.1µm + medium temp. PSG 1,1µm<br /><br />Channel length (gate):<br /><br />N/PDMOS, µm 6 <br /><br />Space line PolySi, µm 8<br /><br />Contacts, µm Ø4<br /><br />Space line Me, µm 12